TITLE: Opportunities and challenges of memristive devices: from device to system level

Special Session Organizers:

Marisa López Vallejo, Universidad Politécnica de Madrid (UPM), Spain

Antonio Rubio, Polytechnic University of Catalonia (UPC), Spain

Juan Bautista Roldán Aranda, University of Granada, Spain

Summary

Since the fabrication of the first physical memristor at HP Labs in 2008 a lot of interest has been attracted to this area of research. Numerous groups have devoted important efforts to the fabrication, modeling, simulation, circuit design, and development of system applications based on memristive devices. There are many applications of memristive devices: non-volatile memories, neural networks, in-memory computing, cryptography, etc.  However, there is still room for improvement since memristors are well known for their variability and highly non-linear behavior. Proof of this is the set of interesting research pieces we present in this session that we have collected here from different research points of view, from the device to the application level.

TITLE: Hardware Security

Special Session Organizers:

Francisco V. Fernández, Instituto de Microelectrónica de Sevilla (CSIC and Universidad de Sevilla), Spain

Macarena Martínez, Instituto de Microelectrónica de Sevilla (CSIC and Universidad de Sevilla), Spain

Summary

Internet-of-Things (IoT) hardware relies upon technologies and devices that should provide suitable performance and tolerance to manufacturing variability. However, variability can be considered as an advantage instead of as a drawback when dealing with security, which is a key aspect of trusted IoT devices. IoT imposes a number of security risks, however, many IoT devices cannot afford the hardware and power cost of many conventional cryptographic solutions. Silicon physical unclonable functions (PUF) constitute an example towards ultra-low power and low-cost cryptographic primitives, which try to exploit variability to generate secret keys and true random number generators (TRNG).

This session deals with a variety of aspects related to IoT hardware security, from conventional PUF design, to attacks and new approaches to TRNG.

TITLE: Applications of 1D- and 2D-based devices: opportunities and challenges for heterogeneous integration

Special Session Organizer:

Aníbal Pacheco-Sánchez, Universitat Autònoma de Barcelona, Spain

Summary

One-dimensional (1D) field-effect transistor (FET) technologies embrace devices with quasi-ballistic materials and structures as the channel such as carbon nanotubes (CNTs). Two-dimensional FETs are based on channels with layered materials such as graphene (G), transition metal dichalcogenides or black phosphorus. In recent years, proof-of concept 1D and 2D transistors and applications have been successfully demonstrated, specially with carbon-based materials. The integration of emerging device technologies with silicon CMOS platforms is a near-future scenario towards exploiting the best features of two worlds in a single integrated circuit: on top of the silicon platform, an emerging-material platform (e.g., based on 1D- or 2D-transistor technology) could be fabricated for making RF or analog functions exploiting the unique properties of the emerging devices.

Technology groups are doing an important effort nowadays in order to provide large-scale production of emerging technologies, e.g., by creating ambitious pilot lines. Hence, it is an adequate opportunity for device engineers and circuit designers to join efforts in order to complete a collaborative research framework all electronics technology requires to be successful. This session is intended to provide a perspective of the opportunity niches and challenges ahead to scale up these emerging devices to higher Technology Readiness Levels, i.e., to heterogeneous integration, while drawing a collaborative scenario among manufacturers, device modeling engineers and integrated circuit designers.

TITLE: RISC-V and Open hardware: Paving the path for cooperative research, training and innovation around Open-source Hw/Sw

Special Session Organizers:

Francesc Moll, Universitat Politècnica de Catalunya, Spain

Lluís Terés, IMB-CNM (CSIC), Spain

Both organizers are acting on behalf of Red-RISCV,  a Spanish research network collecting members from 14 different research and academic institutions, as well as other groups interested on being associated members, and more than 25 companies aiming to contribute and follow-up the network evolution.

Summary

The RISC-V ISA was born on 2010 at UC Berkeley aiming not just to create a new RISC machine, but an open, advanced, refined and modular instruction set to definitively address the open hardware challenges from the point of view of processor development. In 2016 the RISC-V Foundation came up to guide the open ISA standard independent evolution. Right now, thousands of worldwide members from industry and academia are part of the RISC-V Foundation ecosystem and many hardware implementations of RISC-V ISA have been made available as open source code ready for its physical materialization either in FPGA or in SoC, as well as components at chip level ready for systems development.

Mirroring the software evolution in terms of open source during the last twenty years, it seems clear that open-ISA RISC-V is an excellent opportunity to address open-source hardware for several reasons:

• We must emulate in the hardware world the effect of Linux into software open source.
• Democratize processor development by reducing third party or country dependencies facilitating and opening market competition; thus, reducing the current oligopoly of a few companies.
• Reducing costs by avoiding royalties for the ISA itself and having many different RISC-V providers to choose the best cost-performance solution for each application.
• Although RISC-V does not yet have the large infrastructures of their market competitors (Intel, ARM, AMD), it has very large expectations and interest from both industry and research point of view.
• There is a big opportunity for the research community to work together and develop such an open-hardware ecosystem and infrastructure to address not only RISC-V or processor-based developments, but any SoC or hardware target design.
• The EU Chips Act is betting on open architectures such as RISC-V for its future processors, especially since UK and ARM are no longer part of the European Union and more recently due to semiconductors shortage and related technological sovereignty.
• We have the chance to get involved from the early stages into this new wave of open hardware around RISC-V and beyond it.

This special session aims to open the discussions around open hardware in general including methodologies, specific cases, training, sharing/licensing strategies and any other related topic on this wide domain in order to move towards the open hardware ecosystem. Thus, we expect your contributions on any related topic to have the right picture of our community in this domain.

TITLE: STARDUST: SMART CITY INNOVATIONS

Special Session Organizers:

Ignacio R. Matias, Public University of Navarre, Spain

Jose J. Astrain, Public University of Navarre, Spain

Summary

The technical content of the session is focused on Smart City innovations covering different complementary topics such as IoT, sensors, electrical vehicles, advanced communications, data analytics and cloud computing. The proposal is markedly multidisciplinary, covering several topics of interest to the DCIS audience.

During the special session, the main results of the STARDUST project will be disseminated. STARDUST is an EU Horizon 2020 Smart Cities project, which brings together advanced European cities, thus forming into a constellation of “innovation islands” – exemplary models of smart, highly efficient, intelligent and citizen-oriented cities. However, manuscripts related to Smart City innovations based on the target technologies even outside the STARDUST framework can also be submitted to this session.